News & Updates
Power integrity problems can abound in modern PCBs, especially high-speed boards that run with fast edge rates. These systems require precise design of the PDN impedance to ensure stable power is always delivered throughout the system.
A design project doesn’t appear out of nowhere. The design process spreads over time, and project documents change. Schematic documents gradually become more complex, new functional blocks appear, and already finished parts can be modified and updated.
Capacitance is your friend whenever you need stable power integrity, which is why there is so much focus on decoupling capacitors. While these components are important and they can be used to provide targeted power integrity solutions to certain components, there is one specialty material used to supercharge capacitance in your PCB stackup or package substrate.
The problems you can experience with components and libraries are endless. These problems are the most significant source of design issues and the biggest reason behind respins, costing companies untold amounts of lost profit annually.
If you want to have a better understanding of how to use Altium 365 to maintain a strong and centralized library that is free of problems and headaches, you may want to consider attending this lecture.
As much as we would like to build every high speed PCB perfectly, with ideal SI/PI/EMI characteristics, it isn’t always possible due to many practical constraints. Sometimes a stackup can be “good enough,” even for a high-speed PCB. This always comes from the need to balance engineering constraints, functional requirements, and the need to ensure signal and power integrity in a high-speed design, and finally to ensure compliance with EMC requirements.
When it's time to release your project to your manufacturer, it's essential to ensure that all the necessary design aspects like assembly, BOM, and documentation are accurately and completely conveyed. Consistency is key to ensuring a successful release. Without clear release documentation, the designer faces increased risks of costly manufacturing response, time-consuming rework, or unintentional defects that can make it into the final product.
Involving the whole team that will bring a product to completion early on in the development cycle is vital to efficient development. Design reviews with all the relevant parties are critical at each step of the design process, starting with high-level component selection, then through the schematic capture and PCB layout stages.
Ergonomics and convenience are important issues when designing a printed circuit board and the device as a whole. A lot of Altium Designer tools are aimed at solving them. These include Countersink and Counterbore holes, which allow the use of various types of screws in the mounting holes of the board.
The development of electronic devices always involves the release of many different types of files. And these files are not static - they change as the project progresses. When filling a project with data, a user creates new files, modifies outdated files that have become irrelevant. Managing project data is a separate task, especially for large developments where several participants with different specializations are involved in the process.
Controlled impedance routing at high frequencies is difficult enough, and it's important to make sure that you stay within your loss budget on long routes or in lossy media. When you have to route a long trace or a long differential pair to a connector or another component, what can you do if you're reaching the end of your loss budget? In this article, we’ll take a look at the skip reference routing method and explain how it can help recover some loss budget in a lossy interconnect.
We are pleased to announce that Altium 365 is officially SOC 2 Type 1 certified. System and Organization Controls (SOC) 2 is a widely recognized attestation of security compliance defined by the AICPA and is considered the standard for ensuring data security and operational maturity. A SOC 2 certification provides valuable information for companies to assess the quality of the security provided by a service such as Altium 365.
It’s no secret that component shortages have become more frequent this year. Companies will continue to grapple with supply chain challenges into 2022 and beyond. The impact of manufacturing delays can be substantial if a part is not available. Delays occur and sales plans get put on hold. It can also be very expensive and risky to replace parts from multiple sources. Fortunately, many shortages can be avoided by introducing proactive supply chain practices.
Reliability testing and failure analysis of a PCB/PCBA go hand-in-hand; when designs are stressed to the limit, their failure modes need to be determined through thorough inspection and analysis. To get started on this topic, it’s important to understand the qualification aspects that will govern your bare board design and the PCBA. We’ll look at the various dimensions of PCB/PCBA reliability, as well as some of the standard failure analysis techniques used to identify potential design change requirements.
By now, designers should be aware of some important behavior involved in power delivery to components in a PCB, particularly for digital components. All digital components produce and manipulate wideband signals, where the frequency content theoretically extends up to infinite frequency. As such, some radiation may propagate through your PCB, leading to resonant behavior that is not observed on the power rail.
Once your board passes through the standard PCB fabrication process, the bare copper in your PCB will be ready for the application of a surface finish. PCB plating is applied to protect any copper in your PCB that would be exposed through the solder mask, whether it’s a pad, via, or other conductive element. In this article, I’ll run over the different PCB plating material options and their advantages in your PCB.
The PCB supply chain encompasses multiple components, raw materials, and the PCB itself. PCBs and PCB assemblies are often the most technically complex components that are purchased for electronic assemblies and products. The complexity of modern PCBs leads to several challenges for a supply chain management team that may be significantly different when compared with other commodities the team manages. In this brief guide, we'll look in-depth at the PCB supply chain, and specifically what falls within the purview of a procurement and supply chain management team.
On interconnects, such as board-to-board connections or cascaded transmission line arrangements, you have an important EMC compliance metric that is sometimes overlooked. This is mode conversion, which can be visualized in an S-parameter measurement for differential and common-mode signal transmission. In this article, we’ll look at a short overview of mode conversion in high-speed design with some examples from common differential standards.
There are some aspects of PCB design and layout that seem deceptively simple, and yet they have a complex answer that is related to many important aspects of manufacturing. One of these design aspects is the match between PCB via size and pad size. Obviously, these two points are related; all vias have a landing pad that supports the via and provides a place to route traces into a via pad. However, there are some important sizing guidelines to follow when the matching pad and via sizes, and this match is an important element of DFM and reliability.
Are you looking for a free tool that you can use to calculate the impedance of differential microstrips? We created a simple tool you can use to calculate differential microstrip impedance for a given geometry and dielectric constant. If you’ve been looking for an accurate differential microstrip impedance calculator, then the calculator below is certainly one of the best free tools you’ll find on the internet before you start using field solvers to determine differential pair impedance.
In this article, we’ll discuss the key design features to implement, and steps to take prior to fabrication that will help prevent some common DFM problems. I’ll also provide examples of where I commonly see these PCB DFM problems in signal integrity circuits.
If you’re working with a high-speed digital component, there are some simple power integrity rules that should be followed. However, there is one quantity that is sometimes ignored when building a PDN impedance simulation: the spreading inductance of your plane pair. Here are some points designers should know about the spreading inductance of a plane pair.
In this article, I’ll present some design basics that every new designer should follow to help ensure their design process is successful. Some of these points may challenge the conventional view of how circuit boards are constructed, but they are intended to help balance low noise signaling, manufacturability, and ease of solving a layout.
High voltage PCBs are subject to certain safety and reliability concerns that you won’t find in most other boards. If your fabrication house specializes in high voltage PCBs and keeps materials in stock, they can likely recommend a material set, as well as a standard stackup you might use for certain voltage ranges and frequencies. If you need to choose your own materials, follow the tips below to help you narrow down to the right material set.
There are some guidelines I see many designers implement as a standard practice, often without thinking about it. Some of these practices are misunderstood or implemented without best practices. Others are implemented without thinking about the potential problems. One of these is the use of tented vias, which is sometimes implemented in a PCB layout by default. Is this always the right practice?
The idea of a purely capacitive load is something of a fallacy. Yes, capacitors exist, but all capacitors are non-ideal, and it is this deviation from a theoretical capacitance that determines how to impedance match a load that exhibits capacitive behavior. Let’s take a look at this important aspect of interconnect design and see what it really means to terminate a capacitive load.