News & Updates

Harness Draftsman now supports splitting connection tables across multiple pages in *.HarDwf documents. With the new page height limit setting, you can easily control how much of the table appears on each page.

Discover how the future of automotive electronics is being shaped by a more connected development approach that unifies teams, data, requirements, design, collaboration, and manufacturing. Recorded at BMW Welt and the BMW Museum during Altium’s "The Future of Electronics Development in Automotive" event, this video explores the key challenges and innovations driving the next generation of automotive design.

Soon, PCB design rules in Altium will be organized into reusable Rule Sets within the PCB Rules and Constraints Editor. These rule sets can be created, duplicated, enabled or disabled, renamed, deleted, imported, and exported, making it easier to manage rules for specific interfaces, manufacturing requirements, or unique design constraints.

Check out this video, a follow-up to the decoupling capacitor placement series, exploring the inductance tradeoffs between trace routing and via connections. Using real component examples from an Ethernet switch design in Altium, the video demonstrates how different routing choices can impact overall performance.

The Interactive Length Tuning tool allows you to manually tune a single net in a differential pair while maintaining equal pair length and phase alignment across the entire route. This enables more efficient differential signal transmission, greater control during manual tuning, and faster pattern creation within defined phase tolerance limits.

The question is: Can AI really route a PCB as well as an experienced human designer? In this video, we set out to find the answer. Our expert, Zach Peterson, puts it to the test in a side-by-side layout review. The challenge is based on a LinkedIn post where viewers had to guess which board was AI-generated and which was designed by a human.

Check out the video where we showcase enhanced wire bonding features, including precise bond wire shape definition, improved clearance checking, streamlined import and export workflows, and efficient management of wire bonding objects.

You can now precisely control what design data is included in your ODB++ outputs for different manufacturing recipients. Choose which signal layers to export, decide how the netlist is handled (included, disabled, or neutralized), and control whether component data is removed or shared without properties.

Watch our latest customer success story to see how Proper Voltage partnered with Altium to accelerate high-power battery development for next-generation robotics. With our software, they streamlined collaboration, sped up design reviews, improved sourcing visibility, and reduced risk.

You can now control the vertical spacing of a pin’s designator and name with a custom margin. This setting can be applied globally via Schematic Preferences or adjusted individually in the Pin properties.

Our new video tackles common questions about capacitor placement on a PCB. Expert Zach Peterson explains why placement is often less critical on multilayer boards with well-designed power and ground planes and shares the key insights most application notes leave out.

Watch the video where you can find how Proper Voltage centralized communication, synchronized ECAD–MCAD development, and gained early insight into supply chain risks using Altium’s connected design platform.

The Z-axis clearance rule enables accurate verification of minimum interlayer copper spacing. It supports targeted constraints between net classes, differential pairs, and schematic parameter directives for advanced rule definition.

Watch our latest video to learn what parameterization really means, why getting the manufacturer name and part number right is essential, and how to quickly identify inconsistencies across your schematic components using Altium’s Parameter Manager tool.

The default value for the Solder Mask Expansion rule has been updated to improve consistency across design environments. In both PCB documents and rule-driven solder mask expansion within PCB library documents, the default setting is now 0 mil, replacing the previous default of 4 mil.

Explore the concept of via dispersion and how it impacts propagation delay across frequencies. This tutorial walks through the math behind extracting delay from insertion loss and return loss S-parameters and explains why results can vary depending on your operating range.