News & Updates

High frequency PCB design can seem esoteric, and I've heard many an engineer describe it as "black magic"! The subject is also a bit confusing, especially once someone asks which frequencies could be reasonably considered "high". Before you do anything inside the layout for a high-speed or RF PCB, you will need to pay attention to the materials being used in the board. If you're unsure which high frequency PCB materials you should use, then keep reading to learn more.

Of all the noise and operational challenges designers face in their PCBs, there is one overarching problem that is arguably most popular: electronic noise. It could originate as an SI/PI problem, it could possibly arise from some external source, or it could be good old-fashioned crosstalk! These tend to fall into three categories: adding shielding, doing something to create isolation, or placing filters. Let's look at all of these as they tend to be the default solution set when confronted with many noise problems.

In February, we hit a new record in the number of users on the platform. The Altium 365 user community is now 20,000 strong! You can now migrate from an external version control system to Altium 365 preserving the history of commits. We also received the SOC 2 Type 1 certification from KPMG, made layer stack available in the web viewer, and added the brand new capability to track tasks in the context of your design project. Keep reading to learn more!

Rigid-flex in Altium Designer starts with designing a manufacturable PCB layer stack complete with via transitions and any calculated impedance requirements. Flex sections also need to be placed in the layer stack before moving into the PCB layout. Once inside the PCB editor, bending lines can be clearly defined in the PCB layout, and these can be visualized in Altium Designer's 3D PCB design tools. Keep reading to see how Altium Designer supports your flex and rigid-flex designs.

In the business of PCB design, communicating needs to manufacturers and vendors is a top priority. The context of our requests is sometimes lost either by not providing the correct information, not listing enough information, or not giving any information. Although the experienced PCB designer can take steps to specify everything they want to see in their PCB stackup, eventaully the manufacturer will handle that decision in an effort to balance available materials with processing capabilities and yield.

During the recent IPC APEX expo, there was a lot of discussion about SAP, or semi-additive PCB processes.  As with any new technology adoption there were people that are excited to jump right in and start designing with much finer feature sizes and work through the inevitable changes to the traditional thought process. Others are in a "let’s wait and see" mode and of course there are a few skeptics there as well, so keep reading to learn more.

Parasitic extraction: the integrated circuit design community must grapple with this task on a daily basis, especially once gate features are reduced below ~350 nm and chips run at high switching speeds. The PCB community also has to deal with this idea in order to better design power delivery networks, interconnects with precise impedance, and properly quantify crosstalk and coupling mechanisms.

Most designers don’t realize they need to worry about power integrity until they have a power integrity problem. Other designers might build boards that can’t handle the demands of modern digital and high frequency components, and they may not realize the problems that lurk in their power delivery network (PDN). Although the basic concepts involved in designing for power integrity are well-known, myths about power integrity abound, and designers need tools to help them evaluate and qualify power integrity in a PDN.